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Update 30/4/15:

SFARDS is now opening up the ASIC SF3301's datasheet for developers and anyone interested in the technology.

allow numerous developers to test  new technology in a variety of environments, allowing for a truer test of the SF3301's boundaries and possibly finding an even more optimal running condition.

In addition to this they have made a number of sample chips available, more details including pricing to be released on 4th May.

Datasheet download website as follows:https://github.com/sfards

Specifications:

l 160 BTC Units
l 31 LTC Units
l BTC mode up to 80GH/s with 0.31W/GH
l LTC mode up to 1.89MH/s with 2.0W/MH
l Dual-Mining mode: 100GH/s BTC & 1.75MH/s LTC
l Highly integrated with PLL and Pre-Calculation Engine of BTC
l 2-wires UART interface
l Support Crystal and Oscillator
l Fully adjustable clock frequency
l Support body-bias adjust
l On-chip thermal sensor

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